1. Field of the Invention
This invention relates to improvements in integrated circuits, and more particularly to improvements in integrated circuits for controlling a mass storage peripheral device.
2. Relevant Background
Mass storage peripheral devices have played a large part in the development of modern computers. Typical mass storage devices include hard and floppy disk drives, CD-ROM drives, DVD devices, and the like.
A typical mass storage peripheral device that may be associated with a computer has various electronic circuits for the operation of the device that are configured so that the device may be used as universally as possible with various processor or computer configurations. Typically, for example, a mass storage peripheral device is constructed with a spinning data medium on which data is at least read, and often times to which data may be written. Such devices also generally include a motor for spinning the medium, and one or more head devices that are movable to selectable locations on the medium to read and record data from the medium. Associated electronic circuitry is often provided on a printed circuit board that is provided in an assembly with the spinning medium to control the rotation of the motor and the selective positioning of the heads.
Particular electronic circuits that may be provided with any particular mass storage device may vary depending upon the type and kind of peripheral device considered. Typical electronic circuitry, for example, for a hard disk drive (HDD) assembly may include a servo or motor control circuit for spinning the motor, voice coil control circuitry for positioning the data heads, data preamplifier circuitry for amplifying the signals read by the heads from the spinning medium, read channel processing circuitry for initial processing of the read data, and controller circuitry. The controller circuitry may include buffer memory elements for speed matching and signal timing, signal interfacing circuitry for interfacing the data and other signals to the computer bus and control circuits, error correction and control circuitry, and so on. Such circuitry is generally provided in a number of integrated circuit devices, perhaps contained in as many as nine separate integrated circuit chips, mounted on the printed circuit board that is associated with the particular peripheral device.
The hard disk drive electronics is typically connected by one or more buses to corresponding buses on the "mother board" of the host computer. The mother board may have its own supporting electronics for such peripheral devices, such as line driver circuitry and data processing circuitry to route and control the various signals provided to and from the peripheral device.
Because each particular mass storage peripheral device may have its own particular hardware and software characteristics that may be unique to it, typically, mass storage devices may also be required to include their own customized firmware that enable the associated computer to be properly initialized to address and access the data of the device. Among other things, such firmware may include such information as to how addresses are translated from the computer to the particular arrangement of the mass storage device, such as the cylinder, head, sector, zone, of the device, and so on. Such peripheral devices are supplied with custom firmware that is generally loaded upon initialization of the associated computer into the system RAM.
In most cases, software drivers also may be required. Such software drivers may be provided by generic drivers, often supplied with the computer operating system software, and in other cases, the drivers may be separately provided by the manufacturer of the particular peripheral device, particularly when the particular peripheral device has special or unusual characteristics. Therefore, it can be seen that there are limitations on the variations, particularly on the hardware, that may be provided on any peripheral device, as they must be compatible with existing computer hardware architectures and designs.
As speed of data access increases, hardware and software techniques have been developed to speed up data transfers to and from such mass storage devices. One such technique that is becoming popular is the provision of a Peripheral Component Interconnect (PCI) bus. In addition to providing increased access speed to the data of the peripheral device, the PCI bus is designed to be both processor and computer system architecture independent, with the PCI electrical, protocol, and hardware interface requirements remaining the same regardless of the CPU or host system computer architecture being used. This allows the same peripheral computer device to be connected to a variety different of host systems without requiring different versions of the device for each type of host system with which the device is intended to be used.
PCI bus architecture also allows relocatable expansion ROM location addresses on associated peripheral devices. For additional details of PCI bus characteristics in the context of mass storage peripheral devices, reference is made to PCT application number WO 97/18505, entitled "METHOD AND ARRANGEMENT FOR OPERATING A MASS MEMORY STORAGE PERIPHERAL COMPUTER DEVICE CONNECTED TO A HOST COMPUTER", said application being assigned to the assignee hereof, and incorporated herein by reference.
In addition, mass memory storage peripheral devices may include customized expansion BIOS data that is loaded into the system RAM on initialization of the associated computer. Details of particular BIOS techniques are described in PCT application number WO 97/14095, entitled "SYSTEM FOR PROVIDING BIOS TO HOST COMPUTER", said application being assigned to the assignee hereof and incorporated herein by reference.
One of the goals of mass storage peripheral device manufacturers is to reduce the cost of the devices as much as possible. This has been addressed primarily by increasing levels of electronics integration in concert with decreasing integrated circuit costs for a given function due to decreasing semiconductor geometries. These reductions, however, have not been predominately at the system level. It can be seen that using this approach the required electronic and hardware requirements simiar to a PCI bus.